As is well known, the wafers of power devices may be asymmetrically blocked ("AB") by a fairly thin (e.g., 15 v/um) wafer of epitaxially grown silicon on top of thick, highly doped substrate which provides the mechanical strength for processing. However, epitaxially grown wafers are expensive, and the yield diminishes with increasing thickness. For a MOS processible epitaxially grown wafer, the practical thickness limit is approximately 150 um to 200 um.
As is also well known, the wafers of power devices may also be symmetrically blocked ("SB"). However, the formation of vertical SB devices is nearly impossible because the reverse blocking junction is formed at the epitaxial-substrate interface.
It is desirable that the wafers used in the manufacture of both AB and SB devices be inexpensive, flat and contain minimum impurities. High voltage devices and virtually all SB devices are made from high resistivity single crystal silicon (predominantly float zone). Moreover, the exposure of the back of the wafer to processing permits the enhancement of performance by the use of backside shorts or gates for various purposes, which processing for SB devices may be similar to the frontside processing for high breakdown.
Such wafers must have sufficient thickness for processing, e.g., 15 to 20 mils or more. Thickness is not a problem for high voltage devices because the thickness is needed to support the voltage. However, the device forward drop and switching speed and losses are significantly and adversely affected by excess device thickness.
It is accordingly an object of the present invention to obviate the thickness problems of known methods of manufacturing power devices and to provide a novel method of processing wafers of a desired thickness less than the thickness necessary to provide the required mechanical strength.
In general, the silicon wafer of the desired thickness is bonded to a carrier wafer until most, if not all, of the processing steps are completed, after which the silicon wafer is separated from its carrier wafer.
In one aspect, the carrier wafer may serve as a diffusion source. In another aspect, the areas of the bonding of the silicon wafer to the carrier wafer are selected consistent with the devices or groups of devices to be formed by the separation of the two wafers.
In another aspect, the carrier wafer may by bonded to the device wafer over nearly the full surface area and the carrier wafer remain a part of the final device. In such devices, emitter regions formed in the backside of the device wafer may be electrically connected via a metallic silicide used for bonding to provide backside short circuits between the emitters and an improved performance.
In still another aspect, additional contacts for the backside of the device may be obtained by removing a portion of the carrier wafer so that the top of the carrier wafer may serves as a means for contacting different zones on the back surface of the device wafer.
Further, an antiparallel diode useful in almost all switching applications may be formed at the periphery of the device. Since the bond may not be very thick, a heavy but shallow diffusion into the carrier wafer of the same semiconductor type as used for the emitters of the device wafer assists the remaining diode current.
Where it is desirable to use near full bonding of device and carrier wafers in SB power devices of substantial thickness, the device wafer is easier to handle and the thickness of the carrier wafer may be reduced. In such devices, a lateral voltage capability may be built in and the carrier wafer need not be separated from the final device. Where the carrier wafer is to remain attached, it must have a high resistivity and have regions with sufficient resistivity to deal with high breakdown voltages. This may be accomplished by the creation of a well in the carrier wafer of a conductivity type the same as that of the emitters in the device wafer prior to the bonding of the two wafers, the regions being connected through a metallic bond.
However, where a single carrier wafer would be too thick for good diffusions to meet with sufficiently low resistivity, the carrier wafer may comprise two carrier wafers, i.e., a thin one with the well and reduced series resistivity, and a supporting wafer of the same conductivity.
It is accordingly an object of the present invention to provide a novel semiconductor device and method in which the device and carrier may be preformed and bonded together into a final device.
It is a further object of the present invention to provide a novel semiconductor device and method in which carrier wafer may be formed of two separate wafers.
The bonding of wafers is well known and includes oxide-to-silicon, oxide-to-oxide, and silicon-to-silicon bonding may be used. However, such bonding requires high temperature and/or high pressure.
It is another object of the present invention to obviate the need for high temperature and/or high pressure bonding techniques in the bonding of wafers, and to provide a novel method of bonding wafers for processing.
In one aspect, the bonding of the present invention is selected to provide only the mechanical and thermal performance required by the processing steps. In another aspect, the use of an intermediate material to form a silicon bonding compound at more moderate temperature and/or pressure is preferable.
These and many other objects and advantages will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of preferred embodiments.